Many processing systems implement linear memory addresses while utilizing memories that are logically and physically arranged in a multiple-dimension, hierarchical manner. To illustrate, dynamic random access memories (DRAMs) and other multiple-bank memories often are organized as multiple memory chip modules, each memory chip module having multiple banks, and each bank being arranged by rows and columns. As such, processing systems typically utilize a single, permanent translation policy to translate a linear memory address into various chip, bank, row and column identifiers for selecting the particular chip module, bank, row and column corresponding to the linear address (a process generally referred to as interleaving). One conventional interleaving policy is a low order interleave (LOI) whereby the least significant bits of the linear address are designated as the bank address used to select the bank (e.g., ADDR[1:0] for memory having four banks per chip module), and to select the row address, column address and chip address from the higher order bits of the linear address. Another conventional interleaving policy is a high order interleave (HOI) whereby the most significant bits of the linear address are designated as the bank address used to select the bank (e.g., ADDR[31:30] for memory having four banks per chip module and a thirty-two bit address space), and to select the row address, column address and chip address from the lower order bits of the linear address.
DRAMs and other multiple-bank memories often incur significant delays when switching between rows of a given bank due to the latencies involved in closing one row and opening the next row of the bank. Typically, each bank can maintain one open row that can be accessed with little or no time penalty, so generally it is advantageous to organize memory accesses so that proximate memory accesses access the same page of any given bank. However, the use of the same permanently fixed interleaving policy for different program streams often results in memory access inefficiencies as a given interleaving policy may work well with one program stream to reduce the occurrence of proximate memory accesses to different rows of the same bank, but the same interleaving policy may result in significant page thrashing for another program stream that accesses memory in a different manner that causes frequent accesses to different rows of the same bank under the same interleaving policy. Accordingly, an improved technique for memory address interleaving in multiple-banked memories would be advantageous.